CONTROLLER_RESET=NO_CHANGE, CEATA_DEVICE_INTERRUPT_STATUS=DISABLED, INT_ENABLE=DISABLE_INTERRUPTS, SEND_AUTO_STOP=CLEAR_THIS_BIT_IF_TH, FIFO_RESET=NO_CHANGE, SEND_CCSD=CLEAR_BIT, DMA_RESET=NO_CHANGE, USE_INTERNAL_DMAC=HOST, SEND_IRQ_RESPONSE=NO_CHANGE, ABORT_READ_DATA=NO_CHANGE, READ_WAIT=CLEAR_READ_WAIT
Control Register
| CONTROLLER_RESET | Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets: - BIU/CIU interface - CIU and state machines - abort_read_data, send_irq_response, and read_wait bits of Control register - start_cmd bit of Command register Does not affect any registers or DMA interface, or FIFO. or host interrupts. 0 (NO_CHANGE): No change. 1 (RESET): Reset. Reset SD/MMC controller |
| FIFO_RESET | Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks. 0 (NO_CHANGE): No change. 1 (RESET): Reset. Reset to data FIFO To reset FIFO pointers |
| DMA_RESET | Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks. 0 (NO_CHANGE): No change. 1 (RESET): Reset. Reset internal DMA interface control logic |
| RESERVED | Reserved |
| INT_ENABLE | Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set. 0 (DISABLE_INTERRUPTS): Disable interrupts 1 (ENABLE_INTERRUPTS): Enable interrupts |
| RESERVED | Reserved. Always write this bit as 0. |
| READ_WAIT | Read/wait. For sending read-wait to SDIO cards. 0 (CLEAR_READ_WAIT): Clear read wait 1 (ASSERT_READ_WAIT): Assert read wait |
| SEND_IRQ_RESPONSE | Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state. 0 (NO_CHANGE): No change 1 (SEND_AUTO_IRQ_RESPON): Send auto IRQ response |
| ABORT_READ_DATA | Abort read data. Used in SDIO card suspend sequence. 0 (NO_CHANGE): No change 1 (ABORT): Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence. |
| SEND_CCSD | Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked. NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS. 0 (CLEAR_BIT): Clear bit if the SD/MMC controller does not reset the bit. 1 (SEND_COMMAND_COMPLET): Send Command Completion Signal Disable (CCSD) to CE-ATA device |
| SEND_AUTO_STOP | Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit. 0 (CLEAR_THIS_BIT_IF_TH): Clear this bit if the SD/MMC controller does not reset the bit. 1 (SEND_INTERNALLY_GENE): Send internally generated STOP after sending CCSD to CE-ATA device. |
| CEATA_DEVICE_INTERRUPT_STATUS | CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit. 0 (DISABLED): Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register) 1 (ENABLED): Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register) |
| RESERVED | Reserved |
| CARD_VOLTAGE_A0 | Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented. |
| CARD_VOLTAGE_A1 | Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented. |
| CARD_VOLTAGE_A2 | Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented. |
| RESERVED | Reserved. |
| RESERVED | Reserved. Always write this bit as 0. |
| USE_INTERNAL_DMAC | SD/MMC DMA use. 0 (HOST): Host. The host performs data transfers through the slave interface 1 (DMA): DMA. Internal DMA used for data transfer |
| RESERVED | Reserved |